The scaling of VLSI circuits is a constant effort. Smaller integrated circuits allow more devices to be formed in one semiconductor chip. Additionally, power consumption and performance are also improved. With circuits becoming smaller and faster, improvement in the device driving current is becoming more important, which can be increased by improving carrier mobility. Among efforts made to enhance carrier mobility, forming a stressed channel region is a known practice. The performance of a MOS device can be enhanced through a stressed-surface channel. This technique allows performance to be improved at a constant gate length without adding complexity to the circuit fabrication or design.
Research has revealed that a bi-axial in-plane tensile stress field can improve NMOS performance, and a compressive stress parallel to the channel length direction can improve PMOS device performance. A commonly used method for applying stress to the channel region is forming a stressed contact etch stop layer (CESL) on a MOS device. The stressed CESLs introduce stress into the channel region. Therefore, the carrier mobility is improved. Typically, thick CESLs are preferred since thicker CESLs apply greater stresses in the channel regions of MOS devices. Another commonly used method is forming stressors in source/drain regions. The stressors typically have lattice constants different from that of the semiconductor substrate in which the MOS devices are formed.
The scaling of integrated circuits, however, encounters a problem with such a method. FIG. 1 illustrates a modeling of the resistances in a MOS device. The resistances include four portions, a contact resistance Rco, an extension resistance Rextension, an overlap resistance Rol, and a channel region Rchannel. FIG. 2 illustrates a trend reflecting the weight of an external resistance Rext, which equals (Rco+Rextension+Rol), with respect to the channel resistance Rchannel as a function of the technology nodes. It is found that for 130 nm technology or greater, external resistance Rext is small compared to the channel resistance Rchannel. With the scaling of integrated circuits, Rext becomes increasingly greater with respect to the channel resistance Rchannel. Since the device drive current is inversely proportional to the total resistance (2Rext+Rchannel), the increase in drive current is at least partially offset by the increase in external resistance Rext. When technologies evolve to 65 nm and beyond, the benefit of stressing channels to increase device drive currents is so small that the benefit will no longer be worth the process complexity introduced for generating stresses. It is also expected that in 45 nm technology and below, extension resistance Rextension will far exceed channel resistance Rchannel. Beyond 45 nm technology, Rext becomes the bottleneck for further improvement of device performance. Since contact resistance Rco plays an important role in Rext, it must be reduced in order to continue improving the device performance, especially when the gain comes from strained silicon. A semiconductor device that may overcome the previously discussed deficiencies of the prior art is thus needed.